| 1110 |
FSM verification: erroneous duplicate object name message |
7.1.8 |
FSM verification will result in an error if a state name is the same as port name even if a name space is defined for the FSM so the state name will be different. |
| 1109 |
Type conversions for diagram ports |
7.1.8 |
In EASE 7.0 it was possible to specify a type conversion for a diagram port. In EASE 7.1 this is no longer possible. |
| 1108 |
Print Properties dialog fails |
7.1.8 |
The Print Properties dialog is not shown when the user does not have administrative rights. |
| 1107 |
Changed Verilog FSM State generation |
7.1.7 |
FSM States in Verilog are now defined with a PARAMETER statement. For the enumerated encoding an ranged parameter is defined. |
| 1106 |
Entity not modified after deleting configuration |
7.1.7 |
An entity was not set modified after deleting a configuration. If the entity was not modified another way the configuration would reappear after a project load. |
| 1105 |
Click To Edit Record Align port/generic list of a component map. |
7.1.7 |
Please align ports and generics in the VHDL component map. |
| 1104 |
Scriptum opens many empty HDLFlow windows |
7.1.6 |
Sometimes, when no HDLFlow window is open Scriptum opens many empty HDLFlow windows |
| 1103 |
Linter not run |
7.1.6 |
The linter was not run on a diagram containing warnings. |
| 1102 |
Update & Compile fails on files containing spaces. |
7.1.6 |
The 'Update & Compile from the toplevel marker' fails on files containing spaces. |
| 1101 |
VHDL import of use clause before an architecture |
7.1.6 |
A USE clause before an architecture should be moved to the entity upon VHDL import. |
| 1100 |
Relative path of an external user package or file fail |
7.1.6 |
Ease does not properly handle a relative file path for user packages and external HDL files. |
| 1099 |
HDL Import dialog has poor performance on a large amount of files |
7.1.6 |
The dialog is slow when large amount of files are moved into the selected file area. |
| 1098 |
MetaGeneric not present in the Entity SVG/HTML view |
7.1.6 |
The SVG picture of an Entity still showed the seperate generics when a meta generic was used. |
| 1096 |
Subversion username & password |
7.1.5 |
Add the possibility to specify the Subversion username and password. |
| 1095 |
Module filename contains module body part. |
7.1.5 |
When the file generation mode is all units separatly and hdl is generated for a module, the derived filename contains the module body part. |
| 1094 |
Generic range specification lost on linked entity. |
7.1.5 |
When the actual value of a generic/parameter is modified the generic loses it range when the entity/module is in a linked library. |
| 1093 |
Missing Verilog Signed in REG declaration |
7.1.5 |
Older Cadence NCsim versions require the SIGNED attribute to repeated on the register declaration. |
| 1092 |
Vhdl generated for unbound architectures |
7.1.4 |
When generating VHDL hierarchical for an entity Vhdl is also generated for the unbound architectures. |
| 1091 |
Documentation update |
7.1.4 |
The keys 'z' and 'z' are not documented.
Ease only supports the svn:// protocol for Subversion |
| 1090 |
Improved License Wizard |
7.1.4 |
The license wizard needs to connect to the HDL Works website to directly mail the request to HDL Works. |
| 1089 |
Html generator can fail for Generate Blocks |
7.1.4 |
The HTML generator can crash Ease when generated blocks are present in a block diagram. |
| 1088 |
Compiled packages treated as regular package |
7.1.3 |
Compiled packages (math_real and math_complex) are treated as regular packages causing verification errors. |
| 1087 |
Reduce size of generated HTML |
7.1.2 |
The generated HTNL is quite large when the HDL is generated with the options all in one file. |
| 1086 |
Option to exclude examples from installation |
7.1.2 |
Add an option to the install procedure to exclude the examples. |
| 1032 |
Allow index/range specification for CBN tags |
7.1.1 |
Allow specification of an index/range for CBN tags. Now you need to create a net using wires to add a bus ripper, but this is not always convenient. |
| 928 |
Add indexed name to connect-by-name tag |
7.1.1 |
It should be possible to add indexed names [e.g bus(2)] to a connect-by-name tag to improve the readability of the diagram. |
| 597 |
Define a color for a state |
7.1.1 |
It would be nice if you could change the color of a state. |
| 361 |
Net properties are not derived from bus rippers |
7.1.1 |
When a net is drawn from a bus ripper that has a range, then the net properties (f.e. the range) is not copied to the net when the net is connected to a process port (or concurrent statement port) or another bus ripper. When connected to a component port... |
| 319 |
Define a color for one particular net |
7.1.1 |
It would be nice if the user could define a color for one particular net, f.e. for the clock or reset signal. Then this net has a different color then the other nets. |
| 243 |
Supporting Generate statements on VHDL import |
7.1.1 |
If there is a generate statement in VHDL source code,
the user wants to see this back graphically in EASE when the source code is re-engineered (imported). |
