| 1094 |
Generic range specification lost on linked entity. |
7.0.11 |
When the actual value of a generic/parameter is modified the generic loses it range when the entity/module is in a linked library. |
| 1093 |
Missing Verilog Signed in REG declaration |
7.0.11 |
Older Cadence NCsim versions require the SIGNED attribute to repeated on the register declaration. |
| 1084 |
Riviera support |
7.0.10 |
Improve integration with the Riviera simulator from Aldec |
| 1083 |
Improve net labels |
7.0.10 |
Place net labels for unrouted nets at the first unrouted wire. |
| 1082 |
Vhdl Import fails on multiple clauses in a single use. |
7.0.9 |
Vhdl statement USE ieee.std_logic_1164.all, ieee.std_numeric.all; does not import correctly. |
| 1081 |
Acrobat reader 8.0 does not start with manual. |
7.0.9 |
Acrobat reader 8.0 does not start with any document when specified path is in unix format. |
| 1080 |
External entities with use clauses are inconsistent after an undo. |
7.0.9 |
Package use clauses on an external entity are not cleared after an undo. Leaving the project in an inconsistent state. |
| 1079 |
No fsm clock signal |
7.0.9 |
The fsm clock and clock enable signals cannot be selected after the diagram is cleared. |
| 1073 |
Improved sensitivity for the tooltips |
7.0.8 |
As title |
| 1072 |
New processes/always blocks can be created with an illegal name |
7.0.8 |
New processes or always blocks can have reserved word as identifier. |
| 1071 |
Read only generics can be modified |
7.0.8 |
Component generics of a read only component can still be edited when the diagram is checkout. |
| 1070 |
Deleting a net can cause a crash |
7.0.8 |
Ease can crash when a net and its rippers are both selected and deleted. |
| 1063 |
Replace tags by wires does not initialize net label. |
7.0.7 |
When replacing tags by wires the net label does not get the default settings. |
| 1062 |
Option to disable change propagation to HDL files. |
7.0.7 |
It should be possible to disable change propagation to HDL files |
| 1061 |
Clearing net name not propagated properly. |
7.0.7 |
When clearing the name of a (virtual) net that is connected to a process, the references inside the connected process HDL file will be replaced by an empty string instead of the new virtual name. No undo is possible after this action.
User requests to be... |
| 1060 |
Port selection does not select closest port. |
7.0.6 |
When ports are placed at a single grid distance the selection sometimes doesn't select the closest port. |
| 1059 |
Diagram positions and zoom not properly restored |
7.0.6 |
Depending on how navigation was performed the diagram location was not properly saved and restored. |
| 1058 |
Default browser is not started |
7.0.6 |
IE is always started on Windows Vista |
| 1057 |
Window not visible on desktop after startup |
7.0.6 |
Windows (including Scriptum) are not always visible on the desktop after startup |
| 1056 |
Old HDL code for object in linked design library |
7.0.6 |
After viewing the HDL for an object in a linked library EASE will leave the HDL file in the user directory. When the implementation is changed in the owning project, the project containing the link still shows the 'old' HDL. |
| 1054 |
Math complex and math real vhdl packages are not up to date |
7.0.5 |
As title |
| 1053 |
Windows Vista Compatiblity |
7.0.5 |
The Ease configuration files are not saved at the proper location. |
| 1052 |
Some third party tools do not show up in the tool flow toolbar |
7.0.5 |
Some tool lack the vendor property in the configuration file and therefor do not show up in the toolflow toolbar. |
| 1051 |
FSM labels can only be rotated through the parent popupmenu. |
7.0.5 |
The rotate method on a state machine label foes not rotate the label. |
| 1050 | Wrong port found when wiring |
7.0.5 |
When wiring to a port that is very close to other ports, the wire is sometimes connected to the wrong port. |
| 1049 |
Warning message for Verilog endcase without semicolon |
7.0.5 |
If the user code for an FSM action ends with a Verilog 'endcase' Ease will
issue a warning during verification that the statement does not end
with a semicolon while the semicolon is not needed here. |
1048 |
Declarations before signals generated twice in Verilog |
7.0.5 |
In Verilog mode the Declarations before signals are generated twice |
| 1047 |
New ports are not on the sensitivity list. This will cause linter warnings and undesired VHDL behaviour. |
7.0.4 |
New ports are not on the sensitivity list |
| 1046 |
Ease crashes when merging a net containing a src ripper |
7.0.4 |
Ease crashes when merging nets while the net that is merged contains a src ripper. |
| 1043 |
No default label settings for net created with auto connect ports |
7.0.3 |
When using auto connect ports to create a new net, the new net will not get the default label settings specified in the user options. |
| 1042 |
Crash when trying to create library that already exists |
7.0.3 |
If you try to create a new library but give a name of an existing library, Ease will crash. |
| 1041 |
Unable to change range information for ports |
7.0.3 |
In some cases it is not possible to change the range information for ports that have a vector type. |
| 1040 |
Skeleton not created for HDL architectures |
7.0.2 |
The HDL file skeleton is not always present the first time you enter a HDL file architecture |
| 1039 |
Testbench generator should copy generics |
7.0.2 |
Testbench generator should copy generics to the testbench entity, so that they can be used in range definitions for local signals |
| 1038 |
Monitor process should have sensitive ports |
7.0.2 |
Process/Always ports on the monitor should be level sensitive |
| 1018 |
All HDL files are opened when loading a project |
7.0.1 |
When opening a project all HDL files (for achitectures, packages and processes) are opened. This is a major performance issue when using projects stored on network drives. |
| 1007 |
Propagate portname changes into the HDL Files |
7.0.1 |
Port name changes shoud be propagated into the HDL Files. |
| 1006 |
Hierarchical VCM actions for entities/modules |
7.0.1 |
Add support for hierarchical VCM actions on entities/modules |
| 997 |
Configurable default component name |
7.0.1 |
It would be nice to be able to configure the default component name. Now it is always u<n>, but something like u_<entity name>_<n> would be nicer. |
| 996 |
Improved verification |
7.0.1 |
Ease should issue a warning when trying to connect 2 output ports. In Verilog mode this does not issue any warning at all ... |
| 995 |
Show instantiated from in browser |
7.0.1 |
Currently it is not possible to find out where an entity/module is instantiated. Please visualize this information in the browser. |
| 994 |
Improved visibility of selected nets and wire segments |
7.0.1 |
When selecting a net (e.g. using the diagram find dialog), it is sometimes difficult to find the selected net. The color of the net does not change, but only the nodes are 'highlighted' using the color black. This does not make it easy to spot the... |
| 993 |
Improved visibility of selected objects |
7.0.1 |
After using the find dialog, it is not always easy to find the selected object in the diagram. The selected object should be easier to spot. |
| 990 |
Show branch name for version managed objects |
7.0.1 |
The branch name is not shown for version managed objects: only the version number is shown. The branch name is now shown as info tip in the browser. |
| 984 |
Propagating multiple ports up the hierarchy |
7.0.1 |
Currently it is only possible to propagate one port up the hierarchy. Why is it not possible to propagate all selected ports at once ? |
| 983 |
Connect bus rippers using CBN tags |
7.0.1 |
It would be useful to be able to connect bus rippers using CBN tags and also to be able to use the Open connector on them. |
| 819 |
Connection of tag to bus ripper |
7.0.1 |
It should be nice if you can connect a tag to a busripper. For example to set a constant value on a part of a bus. |
| 800 |
Add command line scripting to generate HDL from previous versions |
7.0.1 |
When using RCS it is hard to find the difference between two Ease project versions. Generating the source from the two versions and a diff will give information about the difference between the two versions. It would be nice when Ease supports command... |
| 619 |
VHDL parser does not check on ranges of connectivity |
7.0.1 |
Create a component with port dbus(4:0) and another component with port dbus(2:0), autoconnect dbus(4:0) and do a verify. The connection to dbus(2:0) is an error in ModelSim, but not in the verify. |
| 643 |
Too many different Scriptum windows |
7.0.1 |
Too many different Scriptum windows are popped up |
| 660 |
Default HDL design flow missing |
7.0.1 |
HDL design flow wizard: Should this be set for every new project? It would be nice to be able to set a default. |
| 552 |
Truth Tables support |
7.0.1 |
As Title |
| 418 |
Automatic Testbench Generation |
7.0.1 |
Automatic Testbench Generation - To automatically generate the skeleton testbench file for a block or design would make life very easy indeed. |
| 391 |
Pop up Edit Port dialog when adding a port |
7.0.1 |
When entering a diagram port (for entity): I select my location, and an "Enter port name" box pops up. I think it would be better if the "edit port" box popped up. Most times I will be adding a comment or a range, so why not save me... |
| 380 |
Possibility to change actual values for more than one generic at a time |
7.0.1 |
It is not possible to change actual values for more than one generic at a time. |
| 142 |
File Open Dialog |
7.0.1 |
- In the "File->Open" directory the directories and projects are mixed, not neatly ordered.
- Directories and files are also sorted in an odd way: first all with capital letters then the rest.
- In the area of the Selected Directory only... |
