FLDL/FTDL to VHDL Translation

Introduction

HDL Works offers you a solution to translate FLDL-E (The Extended Fujitsu Logic Description Language) and FTDL-E (The Extended Fujitsu Test data Description Language) to VHDL.

Using our experience we are able to quickly and accurately translate your existing FLDL/FTDL to VHDL, allowing you to move your designs to other targets or integrate the design into a new project.

The translation is available both as a software program and as a service.

Approach

HDL Works developed sofware that is able to translate the FLDL and most of the FTDL automatically. The resulting VHDL is synthesizable with all major synthesis tools.

Output of the translation

• VHDL design file
• VHDL testbench file containing:
• Testbench entity
• Architecture for each test present
• Vector file(s), one for each test present
• TCL script file to:
• Create libraries work and ftdl
• Compile the ftdl_reader_pkg package file
• Compile the VHDL entity file and testbench file.
• Run simulation for each test.

Benefits

• Design reuse of existing FLDL designs in VHDL
• Single design and test environment for your project
• Automated translation prevents errors made during manual translation
• Translation in seconds instead of days

Limitations

The following (test) constructs described by the keywords below in the FTDL language are currently not supported.

• RAM - ENDRAM
• RAMPIN
• RAMTYPE
• MEASURE - ENDMEAS
• SCAN
• SD
• SPATH
• SELPIN
• WAVE - ENDWAVE

More Information

For more information or a quote on the translation of your FLDL/FTDL to VHDL (or Verilog) please contact HDL Works at .