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22
23 library ieee, cpu6809;
24 use ieee.std_logic_1164.all;
25 use ieee.numeric_std.all;
26 use ieee.std_logic_unsigned.all;
27 use cpu6809.cpu_def.all;
28
29 entity cpu09 is
30 port(
31 address : out std_logic_vector(15 downto 0);
32 clk : in std_logic;
33 data_in : in std_logic_vector(7 downto 0);
34 data_out : out std_logic_vector(7 downto 0);
35 halt : in std_logic;
36 hold : in std_logic;
37 keyboard_irq : in std_logic;
38 rst : in std_logic;
39 rw : out std_logic;
40 timer_irq : in std_logic;
41 trap_irq : in std_logic;
42 uart_irq : in std_logic;
43 vma : out std_logic);
44
45 end entity cpu09 ;
46
47 48 49 50 51 architecture structure of cpu09 is
52
53 component reg_bank
54 port(
55 acca : out std_logic_vector(7 downto 0);
56 acca_ctrl : in acca_type;
57 accb : out std_logic_vector(7 downto 0);
58 accb_ctrl : in pull_type;
59 cc : out std_logic_vector(7 downto 0);
60 cc_ctrl : in cc_type;
61 cc_out : in std_logic_vector(7 downto 0);
62 clk : in std_logic;
63 data_in : in std_logic_vector(7 downto 0);
64 dp : out std_logic_vector(7 downto 0);
65 dp_ctrl : in pull_type;
66 ea : out std_logic_vector(15 downto 0);
67 ea_ctrl : in ea_type;
68 hold : in std_logic;
69 iv : out std_logic_vector(2 downto 0);
70 iv_ctrl : in iv_type;
71 ix : out std_logic_vector(15 downto 0);
72 ix_ctrl : in ctrl_type;
73 iy : out std_logic_vector(15 downto 0);
74 iy_ctrl : in ctrl_type;
75 md : out std_logic_vector(15 downto 0);
76 md_ctrl : in md_type;
77 nmi_ack : out std_logic;
78 nmi_ctrl : in nmi_type;
79 op_code : out std_logic_vector(7 downto 0);
80 op_ctrl : in op_type;
81 out_alu : in std_logic_vector(15 downto 0);
82 pc : out std_logic_vector(15 downto 0);
83 pc_ctrl : in pc_type;
84 pre_code : out std_logic_vector(7 downto 0);
85 pre_ctrl : in op_type;
86 sp : out std_logic_vector(15 downto 0);
87 sp_ctrl : in ctrl_type;
88 up : out std_logic_vector(15 downto 0);
89 up_ctrl : in ctrl_type);
90
91 end component reg_bank ;
92
93 component nmi_handler
94 port(
95 clk : in std_logic;
96 nmi : in std_logic;
97 nmi_ack : in std_logic;
98 nmi_req : out std_logic;
99 rst : in std_logic);
100
101 end component nmi_handler ;
102
103 component alu
104 port(
105 alu_ctrl : in alu_type;
106 cc : in std_logic_vector(7 downto 0);
107 cc_out : out std_logic_vector(7 downto 0);
108 left : in std_logic_vector(15 downto 0);
109 out_alu : out std_logic_vector(15 downto 0);
110 right : in std_logic_vector(15 downto 0));
111
112 end component alu ;
113
114 component sequencer
115 port(
116 acca_ctrl : out acca_type;
117 accb_ctrl : out pull_type;
118 addr_ctrl : out addr_type;
119 alu_ctrl : out alu_type;
120 cc : in std_logic_vector(7 downto 0);
121 cc_ctrl : out cc_type;
122 clk : in std_logic;
123 dout_ctrl : out dout_type;
124 dp_ctrl : out pull_type;
125 ea : in std_logic_vector(15 downto 0);
126 ea_ctrl : out ea_type;
127 firq : in std_logic;
128 halt : in std_logic;
129 hold : in std_logic;
130 irq : in std_logic;
131 iv : in std_logic_vector(2 downto 0);
132 iv_ctrl : out iv_type;
133 ix_ctrl : out ctrl_type;
134 iy_ctrl : out ctrl_type;
135 left_ctrl : out left_type;
136 md : in std_logic_vector(15 downto 0);
137 md_ctrl : out md_type;
138 nmi_ack : in std_logic;
139 nmi_ctrl : out nmi_type;
140 nmi_req : in std_logic;
141 op_code : in std_logic_vector(7 downto 0);
142 op_ctrl : out op_type;
143 pc_ctrl : out pc_type;
144 pre_code : in std_logic_vector(7 downto 0);
145 pre_ctrl : out op_type;
146 right_ctrl : out right_type;
147 rst : in std_logic;
148 sp_ctrl : out ctrl_type;
149 up_ctrl : out ctrl_type);
150
151 end component sequencer ;
152
153 signal op_ctrl : op_type;
154 signal pre_ctrl : op_type;
155 signal acca_ctrl : acca_type;
156 signal accb_ctrl : pull_type;
157 signal ix_ctrl : ctrl_type;
158 signal iy_ctrl : ctrl_type;
159 signal sp_ctrl : ctrl_type;
160 signal up_ctrl : ctrl_type;
161 signal pc_ctrl : pc_type;
162 signal ea_ctrl : ea_type;
163 signal md_ctrl : md_type;
164 signal nmi_ctrl : nmi_type;
165 signal dp_ctrl : pull_type;
166 signal cc_ctrl : cc_type;
167 signal iv_ctrl : iv_type;
168 signal addr_ctrl : addr_type;
169 signal dout_ctrl : dout_type;
170 signal left_ctrl : left_type;
171 signal right_ctrl : right_type;
172 signal left : std_logic_vector(15 downto 0);
173 signal acca : std_logic_vector(7 downto 0);
174 signal accb : std_logic_vector(7 downto 0);
175 signal xreg : std_logic_vector(15 downto 0);
176 signal yreg : std_logic_vector(15 downto 0);
177 signal sp : std_logic_vector(15 downto 0);
178 signal up : std_logic_vector(15 downto 0);
179 signal pc : std_logic_vector(15 downto 0);
180 signal ea : std_logic_vector(15 downto 0);
181 signal md : std_logic_vector(15 downto 0);
182 signal dp : std_logic_vector(7 downto 0);
183 signal cc : std_logic_vector(7 downto 0);
184 signal iv : std_logic_vector(2 downto 0);
185 signal right : std_logic_vector(15 downto 0);
186 signal alu_ctrl : alu_type;
187 signal cc_out : std_logic_vector(7 downto 0);
188 signal out_alu : std_logic_vector(15 downto 0);
189 signal nmi_ack0 : std_logic;
190 signal op_code : std_logic_vector(7 downto 0);
191 signal pre_code : std_logic_vector(7 downto 0);
192 signal nmi_req : std_logic;
193 signal irq : std_logic;
194 signal firq : std_logic;
195 signal nmi : std_logic;
196
197 begin
198
199 u0: reg_bank
200 port map(
201 acca => acca,
202 acca_ctrl => acca_ctrl,
203 accb => accb,
204 accb_ctrl => accb_ctrl,
205 cc => cc,
206 cc_ctrl => cc_ctrl,
207 cc_out => cc_out,
208 clk => clk,
209 data_in => data_in,
210 dp => dp,
211 dp_ctrl => dp_ctrl,
212 ea => ea,
213 ea_ctrl => ea_ctrl,
214 hold => hold,
215 iv => iv,
216 iv_ctrl => iv_ctrl,
217 ix => xreg,
218 ix_ctrl => ix_ctrl,
219 iy => yreg,
220 iy_ctrl => iy_ctrl,
221 md => md,
222 md_ctrl => md_ctrl,
223 nmi_ack => nmi_ack0,
224 nmi_ctrl => nmi_ctrl,
225 op_code => op_code,
226 op_ctrl => op_ctrl,
227 out_alu => out_alu,
228 pc => pc,
229 pc_ctrl => pc_ctrl,
230 pre_code => pre_code,
231 pre_ctrl => pre_ctrl,
232 sp => sp,
233 sp_ctrl => sp_ctrl,
234 up => up,
235 up_ctrl => up_ctrl);
236
237 u3: nmi_handler
238 port map(
239 clk => clk,
240 nmi => nmi,
241 nmi_ack => nmi_ack0,
242 nmi_req => nmi_req,
243 rst => rst);
244
245 u4: alu
246 port map(
247 alu_ctrl => alu_ctrl,
248 cc => cc,
249 cc_out => cc_out,
250 left => left,
251 out_alu => out_alu,
252 right => right);
253
254 u5: sequencer
255 port map(
256 acca_ctrl => acca_ctrl,
257 accb_ctrl => accb_ctrl,
258 addr_ctrl => addr_ctrl,
259 alu_ctrl => alu_ctrl,
260 cc => cc,
261 cc_ctrl => cc_ctrl,
262 clk => clk,
263 dout_ctrl => dout_ctrl,
264 dp_ctrl => dp_ctrl,
265 ea => ea,
266 ea_ctrl => ea_ctrl,
267 firq => firq,
268 halt => halt,
269 hold => hold,
270 irq => irq,
271 iv => iv,
272 iv_ctrl => iv_ctrl,
273 ix_ctrl => ix_ctrl,
274 iy_ctrl => iy_ctrl,
275 left_ctrl => left_ctrl,
276 md => md,
277 md_ctrl => md_ctrl,
278 nmi_ack => nmi_ack0,
279 nmi_ctrl => nmi_ctrl,
280 nmi_req => nmi_req,
281 op_code => op_code,
282 op_ctrl => op_ctrl,
283 pc_ctrl => pc_ctrl,
284 pre_code => pre_code,
285 pre_ctrl => pre_ctrl,
286 right_ctrl => right_ctrl,
287 rst => rst,
288 sp_ctrl => sp_ctrl,
289 up_ctrl => up_ctrl);
290
291
292 addr_mux: process (addr_ctrl, sp, up, pc, ea, iv) is
293 begin
294 case addr_ctrl is
295 when idle_ad =>
296 rw <= '1';
297 vma <= '0';
298 address <= (OTHERS => '1');
299 when fetch_ad =>
300 rw <= '1';
301 vma <= '1';
302 address <= pc;
303 when read_ad =>
304 rw <= '1';
305 vma <= '1';
306 address <= ea;
307 when write_ad =>
308 rw <= '0';
309 vma <= '1';
310 address <= ea;
311 when pushs_ad =>
312 rw <= '0';
313 vma <= '1';
314 address <= sp;
315 when pulls_ad =>
316 rw <= '1';
317 vma <= '1';
318 address <= sp;
319 when pushu_ad =>
320 rw <= '0';
321 vma <= '1';
322 address <= up;
323 when pullu_ad =>
324 rw <= '1';
325 vma <= '1';
326 address <= up;
327 when int_hi_ad =>
328 rw <= '1';
329 vma <= '1';
330 address <= "111111111111" & iv & "0";
331 when int_lo_ad =>
332 rw <= '1';
333 vma <= '1';
334 address <= "111111111111" & iv & "1";
335 when others =>
336 rw <= '1';
337 vma <= '0';
338 address <= (OTHERS => '1');
339 end case;
340 end process addr_mux ;
341
342
343
344 dout_mux: process (dout_ctrl, dp, xreg, yreg, sp, up, pc, md, cc, accb, acca) is
345 begin
346 case dout_ctrl is
347 when md_hi_dout =>
348 data_out <= md(15 downto 8);
349 when md_lo_dout =>
350 data_out <= md(7 downto 0);
351 when acca_dout =>
352 data_out <= acca;
353 when accb_dout =>
354 data_out <= accb;
355 when ix_lo_dout =>
356 data_out <= xreg(7 downto 0);
357 when ix_hi_dout =>
358 data_out <= xreg(15 downto 8);
359 when iy_lo_dout =>
360 data_out <= yreg(7 downto 0);
361 when iy_hi_dout =>
362 data_out <= yreg(15 downto 8);
363 when sp_lo_dout =>
364 data_out <= sp(7 downto 0);
365 when sp_hi_dout =>
366 data_out <= sp(15 downto 8);
367 when up_lo_dout =>
368 data_out <= up(7 downto 0);
369 when up_hi_dout =>
370 data_out <= up(15 downto 8);
371 when cc_dout =>
372 data_out <= cc;
373 when dp_dout =>
374 data_out <= dp;
375 when pc_lo_dout =>
376 data_out <= pc(7 downto 0);
377 when pc_hi_dout =>
378 data_out <= pc(15 downto 8);
379 when others =>
380 data_out <= (OTHERS => '0');
381 end case;
382 end process dout_mux ;
383
384
385
386 left_mux: process (left_ctrl, yreg, xreg, sp, up, pc, ea, md, dp, cc, acca,
387 accb) is
388 begin
389 case left_ctrl is
390 when cc_left =>
391 left <= "00000000" & cc;
392 when acca_left =>
393 left <= "00000000" & acca;
394 when accb_left =>
395 left <= "00000000" & accb;
396 when dp_left =>
397 left <= "00000000" & dp;
398 when accd_left =>
399 left <= acca & accb;
400 when md_left =>
401 left <= md;
402 when ix_left =>
403 left <= xreg;
404 when iy_left =>
405 left <= yreg;
406 when sp_left =>
407 left <= sp;
408 when up_left =>
409 left <= up;
410 when pc_left =>
411 left <= pc;
412 when others =>
413 left <= ea;
414 end case;
415 end process left_mux ;
416
417
418
419 right_mux: process (right_ctrl, acca, accb, ea, md) is 420 begin
421 case right_ctrl is
422 when ea_right =>
423 right <= ea;
424 when zero_right =>
425 right <= "0000000000000000";
426 when one_right =>
427 right <= "0000000000000001";
428 when two_right =>
429 right <= "0000000000000010";
430 when acca_right =>
431 if acca(7) = '0' then
432 right <= "00000000" & acca(7 downto 0);
433 else
434 right <= "11111111" & acca(7 downto 0);
435 end if;
436 when accb_right =>
437 if accb(7) = '0' then
438 right <= "00000000" & accb(7 downto 0);
439 else
440 right <= "11111111" & accb(7 downto 0);
441 end if;
442 when accd_right =>
443 right <= acca & accb;
444 when md_sign5_right =>
445 if md(4) = '0' then
446 right <= "00000000000" & md(4 downto 0);
447 else
448 right <= "11111111111" & md(4 downto 0);
449 end if;
450 when md_sign8_right =>
451 if md(7) = '0' then
452 right <= "00000000" & md(7 downto 0);
453 else
454 right <= "11111111" & md(7 downto 0);
455 end if;
456 when others =>
457 458 right <= md;
459 end case;
460 end process right_mux ;
461
462
463 irq <= uart_irq or keyboard_irq;
464 nmi <= trap_irq;
465 firq <= timer_irq;
466 end architecture structure ; 467
468
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