HDL Companion: Trace View

You can follow a port or signal through the hierarchy and see where it used in the trace view. In the example at the right you see the port clk_i from the module usbf_top being trace down. The references denote where the signal is used in the HDL code. In this example you see that clk_i is connected to wb_clk of module usbf_wb and used as clock signal in 5 always statements.